1. Field of the Invention
The present invention relates generally to reducing switching noise generated by the coupling between adjacent nodes or pins of, for example, an integrated circuit.
2. Description of the Prior Art
As power supply voltage levels continue to drop for integrated circuit products, it becomes more difficult to obtain adequate signal-to-noise ratios for high performance analog circuits. Simultaneously, as integrated circuits are being reduced in size, they require a greater number of input and output pins which results in the pins being located physically closer together. The problem with locating pins physically closer is the consequent increase in inductive and capacitive coupling between adjacent circuit pins. This coupling problem is especially acute in situations where a large number of switching operations take place at one of the nodes, for instance, when the node is utilized for periodic, or non-periodic but clock-synchronous pulses. Such a situation arises when a digital pin, or an analog pin with a large voltage swing, is located adjacent to a circuit pin that is noise sensitive, such as when the adjacent circuit pin is required to maintain a reference voltage or reference current level.
The traditional approach to the problem of cross-coupling was to design the circuit package so as to isolate sensitive pins from those pins that generate excessive cross-coupling. The drawback to this approach is the extensive design effort required to isolate the sensitive pins, which may not even be possible, or the requirement of major changes to existing circuit designs.
In view of the shortcomings in conventional approaches for reducing cross coupling between adjacent pins in integrated circuits, it is an object of the present invention to provide a technique for filtering signals that change slowly compared to the frequency of the signal generating parasitic noise.
It is another object of the present invention to provide a switched capacitor circuit to sample a signal containing recurring noise generated by parasitic coupling from an adjacent switching network at the rate of the switching network so as to sample the signal during times when the signal is not affected by the parasitic coupling.
In accordance with the above objects and additional objects that will become apparent hereinafter, embodiments of the present invention filter a signal subject to parasitic coupling by an adjacent switching network, such as a clock signal or other recurring signal, by passing the signal subject to the coupling through a low pass filter, activating a switch to sample and hold the low pass filtered signal during times that the signal is not affected by the parasitic coupling, and then filtering the sampled signal so as to reduce noise generated by the sampling switch. The sampling switch is activated periodically by the device that is generating the parasitic coupling, such as a clock signal, so that, after a suitable delay or other timing mechanism, the signal is sampled and held at the value that occurs when the signal is not affected by the parasitic coupling. In one embodiment, a switched-capacitor circuit is used to filter out undesired periodic or clock-synchronous noise that is coupled from a switching node to an adjacent noise-sensitive circuit node. Such an embodiment is appropriate for use in applications where a sensitive DC input or slowly changing AC input is constrained to be placed adjacent to a clock-synchronous signal.